1. Field of the Invention
The present invention relates to circuitry for providing electrostatic discharge (ESD) protection. More particularly, the present invention relates to components for providing ESD protection for a circuit with components made using a 2.5 volt semiconductor process having a 5.0 volt compatible CMOS I/O.
2. Description of the Related Art
ESD can occur when a human body, or machine comes into contact with lead pins of a chip before the chip is placed in a circuit. ESD can also occur after the chip is placed in a circuit and powered up when a charged up lead pin is accidentally connected to ground. A typical circuit used to test a chip to determine if the chip offers adequate protection during an ESD event includes a series connected resistor and capacitor. To simulate the human body, a resistance of approximately 3000 .OMEGA. is utilized in the test circuit along with a capacitance of approximately 10 pF. Because the instantaneous voltage from a human body can be as much as 2000 volts, the capacitor is typically charged up to as much as 3000 volts and connected through the resistor to the lead pin of a chip to assure the chip provides adequate ESD protection.
To prevent damage to circuitry on a chip during an ESD event, the output buffers are typically designed to go into avalanche breakdown to connect a lead pin receiving an electrostatic discharge directly to a ground pin without affecting other circuitry on the chip. FIG. 1 illustrates a portion of a typical output buffer of a chip which is powered down. The buffer includes an NMOS pull up transistor 102 and an NMOS pull down transistor 104. During power down, the gates of transistors 102 and 104 are connected to a ground pin through resistors. The transistors of the buffer are also connected to a pad 100 which is coupled to a lead pin of a chip.
When an ESD event occurs providing up to 3000 volts to the pad, transistor 104 goes into breakdown and then snap-back to connect the pad to ground to prevent circuit damage. To describe how snap back occurs during an ESD event to provide ESD protection, reference is made to FIGS. 2 and 3. FIG. 2 shows a cross section of a substrate containing the transistor 104 of FIG. 1. FIG. 3 graphs voltage at the pad vs. current through the source to drain of transistor 104.
In an ESD event, the voltage at the drain region 200 rises quickly. The inductance 201 will limit how quickly voltage rises on the drain region 200. Initially, with a voltage rising on the drain 200, the gate to drain overlap capacitance 208 begins to pull the gate high. The series resistance 210 of the gate initially protects the gate oxide because the voltage drop across the resistor is subtracted from the voltage that would otherwise appear across the gate oxide. As the gate is pulled up, the channel between the drain 200 and source 202 turns on.
The region of highest electric field is the pinch-off region 204 where the conducting electrons reach impact ionization energies, giving rise to electron-hole pair generation. With electroin-hole pair generation, the n+ drain region 200 will further be pulled high, to cause gate aided breakdown by creating a depletion region in the area 204 of the substrate between the gate 206 and region 200. Breakdown occurs initially in region 204 because the highest electric field occurs at this edge of the gate 206. With breakdown initially occurring, electron hole pairs are generated. Holes move away from the pad toward the p- substrate to pull the substrate high. With the p- substrate going high, forward biasing of a diode formed from the p- substrate region to the n+ source region 202 occurs with the n+ region connected to ground through an inductive line 203. With the p- to n+ diode forward biased, electrons will be injected from the region 202 into the p- substrate, which increases the carrier concentration locally. As the carrier concentration increases, the depletion width to maintain a given maximum electric field decreases thus decreasing the voltage drop--hence creating snap back.
As current increases through the transistor 104 beyond a primary breakdown point 300, which occurs at snap back, a secondary breakdown can occur at a point 302 as shown in FIG. 3. Secondary breakdown is destructive to the transistor 104 causing it to essentially melt. The size of transistor 104 is typically set to limit current below secondary breakdown when an ESD event occurs. If the size of the single transistor 104 is insufficient to limit current below secondary breakdown when an ESD event occurs, multiple transistors can be utilized as shown in FIG. 4.
In FIG. 4, three transistors 401-403 are used to connect the pad to ground. With three transistors and no resistors 411-413, when an ESD event occurs, one of the transistors 401-403 will break down first to limit the voltage potential across the source to drain of remaining transistors in 401-403, so the remaining transistors in 401-403 will not turn on. Current will then increase in the transistor which is turned on to cause secondary breakdown in the transistor turned on. To enable all transistors 401-403 to turn on during an ESD event, ballast resistors 411-413 are included in series with the source to drain path of each transistor 401-403. The ballast resistors have resistance values set so that if one of the transistors 401-403 goes into primary breakdown, the voltage applied across the remaining transistors in 401-403 will be enough to turn on those transistors so that current will not increase in one transistor enough to cause a secondary breakdown.
For an ESD event where the pad is pulled negative, referring to FIG. 2, the diode formed by region 200 and the p- substrate will be forward biased causing electron injection into the substrate. A p+ guard region 210 implanted in the substrate near the transistor 104 will complete the circuit to ground and so limits any negative voltage.
The structure for a 5.0 volt compatible output buffer made using a 2.5 volt semiconductor process makes providing ESD protection more difficult. A portion of a 5.0 volt compatible output buffer made using a 2.5 volt transistor process is shown in FIG. 5. The circuit includes two pull down transistors 501-502 with source to drain paths connected in series to connect a pad to ground. The circuit also includes two pull up transistors 503 and 504 with source to drain paths connected in series to connect the pad to a pin power supply voltage Vcc. In operation, when a 5.0 volt difference is applied from the pad to ground, or from Vcc to the pad, voltages are applied to the gates of transistors to prevent a voltage potential difference across any of transistors 501-504 from exceeding 2.7 volts. For example, when 5.0 volts is applied from the pad to ground, 3.3 volts is applied to the gate of transistor 502 to cause a 2.5 volt drop from the pad to node n2. With n2 at 2.5 volts, the gate to source, gate to drain, and source to drain voltages of transistors 501 and 502 do not exceed a maximum of 2.7 volts. Circuitry to control the gate voltage of transistors 501-504, as well as additional circuitry for a 5.0 volt compatible I/O buffer made with a 2.5 volt process, is disclosed in U.S. Patent Application Ser. No. 08/912,763, incorporated herein by reference.
FIG. 6 shows a cross section of a substrate containing either the transistors 503 and 504 of FIG. 5, or transistors 501 and 502 of FIG. 5, with a chip powered down. During an ESD event, when a high voltage is applied to the pad, with the gate of transistor 601 grounded, and the n+ region 616 of transistor 602 grounded, the n+region 610 will be pulled high to initiate gate aided breakdown. With breakdown beginning, electron hole pairs are separated and the holes will move away from the region 610 toward the p- substrate to pull the substrate high. With the p- substrate going high, forward biasing of a diode formed from the p- substrate region to the n+source region 616 occurs, since region 616 is grounded. With the p- to n+ (616) diode forward biased, electrons will be injected from the region 616 into the p- substrate to eventually cause snap back.
However, with transistors 501 and 502 of FIG. 5 spaced close enough to allow snap back for ESD protection, snap back can also occur during normal operation. During normal operation, the source of transistor 501 is grounded, a condition needed for snap back. When the output switches from high to low, current through the source to drain of transistor 502 can give rise to hot carrier generation creating electron-hole pairs that can charge up the p- substrate so that snap back can occur.
To prevent snap back during normal operation, the transistors 501 and 502 of FIG. 5 can be physically separated in the substrate. However, with transistors 501 and 502 physically separated to an extent needed to prevent snap back during normal operation, snap back will not occur during an ESD event. Current during an ESD event sufficient to cause breakdown at a region 611 in FIG. 6, as well as a region 615 will damage circuitry on a chip containing the buffer.
It is, therefore, desirable to provide a new ESD protection mechanism for a 5.0 volt compatible I/O buffer made using a 2.5 volt process, where two series transistors are required from a pad to ground.